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Open-source modules

This page contains the links to open-source repositoies for superconducting EDA modules.


TimEx

TimEx is a netlist-to-Verilog HDL extraction module that finds timing parameters of SFQ circuits. The GitHub repository is https://github.com/sunmagnetics/TimEx​

​TimEx development was supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office grant W911NF-17-1-0120.


JoSIM

JoSIM is an open-source simulation engine for superconducting circuits. It combines the functionality of JSIM and WRSpice. The GitHub repository is https://github.com/JoeyDelp/JoSIM

​JoSIM development was supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office grant W911NF-17-1-0120.


AUTO

AUTO is a suite of modules for SFQ circuit margin and yield analysis and optimization. The GitHub repository is https://github.com/coldlogix/auto

AUTO was developed primarily by Thomas Ortlepp at Ilmenau University of Technology.